FIG. 1 depicts a prior art latch circuit 100 comprising eight MOS transistors 110, 120, 130, 140, 150, 160, 170 and 180. Each MOS transistor has a source, a drain and a gate. Transistors 110, 130, 140, and 160 are preferably PMOS transistors; and transistors 120, 150, 170 and 180 are preferably NMOS transistors. The first and second transistors 110, 120 are connected in series such that a source and drain of the first transistor 110 are connected between a first node 115 and a second node 125 and the source and drain of the second transistor are connected between a third node 135 and the second node 125. The third transistor 130 is connected in parallel with the first transistor 110 so that its source and drain are also connected between the first node and the second node. The fourth and fifth transistors 140, 150 are connected in series such that a source and drain of the fourth transistor 140 are connected between the first node 115 and a fourth node 145 and the source and drain of the fifth transistor 150 are connected between the third node 135 and the fourth node 145. The sixth transistor 160 is connected in parallel with the fourth transistor 140 so that its source and drain are also connected between the first node and the fourth node. The first node is connected to a positive power supply and the third node is connected to ground. The voltage level at node 115 represents a logic high and the ground potential a logic low. Transistors 110, 120, 130 will be recognized as forming a first inverter having an input at the gates of transistors 110, 120 130 and an output at second node 125 and transistors 140, 150, 160 as forming a second inverter having an input at the gates of transistors 140, 150, 160 and an output at fourth node 145. In each inverter, the PMOS pull-up transistors have been doubled to enhance stability of the latch circuit. The inverters are cross-coupled by line 127 from second node 125 at the output of the first inverter to the gates of transistors 140, 150, 160 and by line 147 from fourth node 145 at the output of the second inverter to the gates of transistors 110, 120 130.
The source and drain of the transistor 170 are connected between a data in line 105 and the second node 125. Thus, transistor 170 functions as a write transistor for latch circuit 100. The source and drain of transistor 180 are connected between fourth node 145 and ground. Thus, transistor 180 function as a clear transistor for latch circuit 100. A data out line 185 is connected to node 145.
In operation, latch circuit 100 is cleared by applying a positive signal to the gate of transistor 180 to turn it on. As a result, node 145 is bought to essentially ground potential. Since node 145 is connected to the gates of transistor 110, 120, 130 by line 147, the ground potential is applied to those gates, turning on transistor 110 and 130 and turning off transistor 120. As a result, the potential at node 125 rises to approximately the potential of node 115. Since node 125 is connected to the gates of transistors 140, 150, 160 by line 127, a high potential is applied to these gates, turning off transistor 140 and 160 and turning on transistor 150. As a result, the potential at node 145 which had been brought to ground potential by transistor 180 is now held at ground potential by transistor 150.
Thus, as a result of the clear operation, a high potential is established at node 125 and a low potential at node 145. This is one of the two binary values that can be stored in latch 100. To store this value in the latch, there is no need to do anything after the latch is cleared. Alternatively, if a high potential signal is applied to latch 100 from data in line 105 by turning on transistor 170, the high potential will be applied to node 125 and this high potential will also be applied to the gates of transistors 140, 150, 160 thereby turning on transistor 150 so that the potential at node 145 is approximately ground potential.
On the other hand, if a low potential signal is written to latch 100 after it has been cleared, the low potential signal will be applied to node 125 and this low potential will reduce the voltage at the gates of transistors 140, 150 160, thereby turning on transistors 140, 160 and turning off transistor 150. As a result, the potential at node 145 rises to approximately the potential of power supply node 115. This causes the potential at the gates of transistor 110, 120, 130 to rise, thereby turning off transistors 110, 130 and turning on transistor 120. As a result, the potential at node 125, which had been brought to a low potential by transistor 170 is now held at ground potential by transistor 120. Thus, as a result of the write low operation, a low potential is at node 125 and a high potential at node 145. This is the second of the binary values that can be stored in latch 100.
The circuit of FIG. 1 has the disadvantage that it has a relatively high soft error rate (SER). As a result, this circuit is not an attractive candidate for use in critical memory functions such as memory cells in configuration random access memory (CRAM) where a single erroneous bit in the CRAM may render unusable the programmable logic array (PLA) that is programmed by the CRAM.
In an effort to reduce SER, resistors have been inserted in the feedback paths between the inverters. The resistors dampen disturbances between the nodes and reduce the likelihood that such disturbances would flip the logic state of the circuit. FIG. 2 depicts a circuit 200 that has the same transistors and the same topology as circuit 100. Accordingly, the transistors and nodes of FIG. 2 bear the same numbers as those of FIG. 1 increased by 100. Circuit 200 differs from circuit 100 in that node 225 is connected to the gates of transistors 240, 250, 260 by a feedback resistor 228 instead of lead 127 and node 245 is connected to the gates of transistors 210, 220, 230 by a feedback resistor 248 instead of lead 147. However, it is not practical in conventional CMOS technology to achieve significant resistance values in a small layout area. As a result, feedback resistors are not used in latch circuits for technology nodes less than 0.25 um. Accordingly, there is a continuing need for latch circuits with better SER.